1. Technical Field
The present disclosure relates to a delay-locked loop circuit and a method of clock synchronization, and more particularly to a delay-locked loop circuit integrated in a semiconductor memory device and a method of clock synchronization for the semiconductor memory device.
2. Discussion of the Related Art
FIG. 1 is a block diagram illustrating a conventional delay-locked loop circuit. Referring to FIG. 1, a delay-locked loop (DLL) 100 includes a phase detector 110, a charge pump 120, a variable delay line (VDL) 130, and a delay compensation circuit 140. The phase detector 110 detects a phase difference between an external clock signal CLK_IN and an internal clock signal CLK_OUT to generate an up-signal UP or a down-signal DOWN based on the phase difference. The charge pump 120 generates a delay control signal VCON in response to one of the up-signal UP and the down-signal DOWN. The variable delay line 130 generates the internal clock signal CLK_OUT that is synchronized with the external clock signal CLK_IN. The delay compensation circuit 140 compensates for a phase delay of the internal clock signal CLK_OUT due to a propagation delay through a data path (not shown), and provides the phase detector 110 with the compensated clock signal as a feedback signal SFEED.
A semiconductor memory device, such as a dynamic random-access memory (DRAM), needs a much smaller current to operate in a power-down mode or a self-refresh mode than in an active mode. When the semiconductor memory device operates in the power-down mode or the self-refresh mode, the delay-locked loop of the semiconductor memory device also needs to be operated with a smaller current than in an active mode.
Therefore, there is a need for a delay-locked loop with an adjustable operation current according to operation modes of the semiconductor memory device.